The present disclosure relates to a circuit which prevents an over-voltage from being applied to a semiconductor device, and more particularly, relates to an integrated protection circuit of the semiconductor device which is able to prevent a short voltage pulse, such as an electrostatic discharge (ESD) or an electrical over-stress (EOS), from being applied to the semiconductor device.
Electrostatic discharge (ESD) and electrical over-stress (EOS) are different from each other in a transient electrical pulse width. In particular, the electrostatic discharge (ESD) is discharge phenomenon in which a finite amount of positive charge may rapidly move between two objects having different potentials, and the discharge may be made during several hundred picoseconds (ps) to a few microseconds (μs).
Meanwhile, the electrical over-stress (EOS) is an electrical shock such as an abnormal over-current or over-voltage due to leakage current and voltage of equipment which uses a power source, and the EOS may be produced during a few nanoseconds (ns) to a few milliseconds (ms).
When the ESD or the EOS is generated in CMOS-process products, a thin insulating layer such as a gate oxide film may be destroyed. For this reason, there may be a need of a circuit which may protect the thin insulating layer effectively without an increase of the circuit occupying area.